1. Field of the Invention
This invention generally relates to a device and a method for a semiconductor memory, and more particularly to a device and method for compensating defect in a semiconductor memory.
2. Description of Related Art
Recently, because of the prevalence of the computers, the semiconductor memory device such as non-volatile semiconductor memory has been developed and manufactured.
FIG. 1 is a block diagram of a conventional semiconductor memory structure. Referring to FIG. 1, when the user initiate to read the data stored in the semiconductor memory, the address bus 129 will send a set of address signals to the input address buffer 111; the control signal bus 133 will send a control signal to the control unit 119. The control unit 119 based on the control signal controls the input address buffer 111 to send the address signals to the address decoder circuit 117, controls the address decoder circuit 117 to convert the address signals to a real address, and sends the real address to the memory array 121 and the control unit 119 respectively. The control unit 119 based on the real address controls the sensing circuit 125 to retrieve the data from the memory array 121. The data will be sent to the data bus 131 via the data read/write buffer 127. Hence, the user can read the data from the data bus 131. When the user would like to write the data, the procedure is very similar. The difference is that the data is sent via the data bus 131 and the data read/write buffer 127 into the sensing circuit 125; the control unit 119 based on the real address control the sensing circuit 125 sends the data via the data bus 131 into the memory array 121 for storage.
Referring to FIG. 1, the semiconductor memory includes a power supply circuit 115 and a chip identification circuit 123. The power supply circuit 115 is coupled to the power source VDD to provide the power for the operation of the semiconductor memory. The chip identification circuit 123 is for sending identification signal to show the memory size of the memory array 121.
In the light of the above, the address for accessing the data in a conventional semiconductor is in the memory array. When there is a minor defect in the memory array during the manufacturing process, the conventional memory array become useless, which causes a lower yield rate. Therefore, redundancy is typically built into the array. Redundancy permits one to provide full functionality from an array that has a small number of defects by using redundant portions of the array in place of those portions of the array that are defective. U.S. Pat. No. 5,233,559, for example, describes a redundancy scheme used to provide row redundancy in a nonvolatile memory array.
There are limits to the benefits of providing redundancy. Redundant circuits increase the complexity of a part and also occupy precious chip area within the chip. The more redundant circuits one provides, the more likely it becomes that the number of redundant circuits will exceed the number of defects. In such a case, there will be redundant circuits that are unused. Furthermore, the more redundant circuits one provides, the more likely it becomes that a defect will occur in the redundant circuitry. Moreover, no matter how much redundancy one provides to a circuit, if the number of defects is great, there will be insufficient redundancy to compensate for the defects and restore full functionality. Therefore, a significant number of dice are built that must be scrapped because they contain so many defects that they cannot be brought up to full functionality. The cost of producing these defective chips that must be scrapped is included into the cost of producing the fully functional ones.
Various strategies are known that can be used to compensate for memory arrays that cannot be brought up to full functionality. At the wafer level, U.S. Pat. No. 4,007,452 describes a wafer scale integration system and method for interconnecting a plurality of separate memories (or other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and this connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of increments, one associated with each memory. The signal on the identity bus is incremented by usable memories and this signal is compared to an address on the bi-directional memory bus to select memories in an organized manner. This approach permits one to use a wafer that contains several separate memory arrays even when one or more of the arrays is defective. If, however, a separate memory within the wafer is not fully functional, the operational portions of the partially functional separate memory cannot be used because the entire defective separate memory is disabled.
At the chip level, U.S. Pat. No. 4,376,300 describes a memory system that employs a plurality of partially functional “mostly good” memory chips. For one embodiment, a programmable read only memory (PROM) is programmed to recognize the address of the defective elements of the mostly good memory chips and to cause a redundant memory chip to be selected. For another embodiment, a content-addressable memory (CAM) is employed to provide a new address in response to the addresses of defective elements in the mostly good memories. Although partially functional memory chips can be used if they are mostly good, a small number of defects within a memory chip can render the chip mostly bad and therefore unusable.